The attempt to reduce the size of semiconductor devices built on a silicon-type substrate is ever constant. However, as the size of semiconductor devices are reduced, many problems, whose effects were insignificant in larger devices, can become critical to the efficient operation of the device. One such problem is an area of thin material in a dielectric that is formed over a silicon substrate near an isolation region.
FIG. 1 shows this problem where a substrate 101, an isolation region 103, and a gate dielectric 105 come together. As illustrated, a sharp corner or spike, indicated in FIG. 1 by a dotted circle 107, occurs at the edge of the silicon substrate 101 next to the isolation region 103 (usually a shallow trench isolation (STI)). When a subsequent gate dielectric 105 is formed over the substrate 101, this sharp corner effectively causes the dielectric layer 105 to be thinner over the spike than other areas of the dielectric layer 105. This thinner area can result in many problems as devices are reduced in size.
Illustrative examples of these problems include a parasitic transistor, which, in the prior art, can appear as a double hump behavior in a drain current-gate voltage characterization. Another of these problems is that the STI thin corner will allow a punch-through disturb for non-volatile technologies such as flash devices. Finally, this thin corner can also cause a leaky path for logic technologies.
FIGS. 2A and 2B illustrate a technique that, while it was not designed to help with these problems, may help to slightly mitigate them: a sacrificial dielectric layer 205. FIG. 2A illustrates a structure comprising a substrate 101 that has STIs 103 formed within it. FIG. 2B illustrates a sacrificial layer 205 being formed over the substrate 101 and also over portions of the STIs 103. The sacrificial layer 205 is subsequently removed from the substrate 101 and the STIs 103 through an etching process.
While the sacrificial layer 205 is meant to be used as either a screening layer for a subsequent implantation or to remove surface defects from the surface of the substrate 101, FIG. 3 illustrates the effect of the sacrificial layer 205 and its subsequent etching removal on the sharp edges around the STIs 103. As illustrated, the process works to blunt the sharp edge of the substrate 101, and accordingly, to slightly increase the thickness of the dielectric layer 105. However, this unintentional side effect of the formation and subsequent removal of the sacrificial layer 205 cannot, by itself, blunt the edge of the substrate 101 enough to overcome the potential problems with parasitic transistors, leakage, and disturb problems that could come from these areas.
Because of these and other problems associated with the current methods of manufacturing, a new method of reshaping a silicon surface is needed.